Senior Verification Engineer

The Verification Engineer will be a part of the Valens VLSI group. He /She will be responsible for planning (architecture) and developing (coding) all the needed simulation environments for tests and debugs.
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DESCRIPTION

 

The Verification Engineer will be a part of the Valens VLSI group. He /She will be responsible for planning (architecture) and developing (coding) all the needed simulation environments for tests and debugs.

The simulation environments are used to develop new RTL blocks, Full-chip integration, FPGA code and also to debug and resolve bugs found.

 

REQUIREMENTS

 

  • BSC in Electrical Engineering – from a well-known university.
  • At least 5 years’ experience.
  • Knowledge in Specman – an advantage.
  • Knowledge in UVM – an advantage.

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